--inv rundy 32
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity invrunda32 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		rdk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end invrunda32;

architecture Behavioral of invrunda32 is
component keymix is 
    Port ( kid : in  STD_LOGIC_VECTOR (127 downto 0);
		kik : in STD_LOGIC_VECTOR (127 downto 0);
		ko : out  STD_LOGIC_VECTOR (127 downto 0));
end component keymix;

component InSbox7set is
    Port ( si : in  STD_LOGIC_VECTOR (127 downto 0);
		so : out  STD_LOGIC_VECTOR (127 downto 0));
end component InSbox7set;

signal n1, n2 : STD_LOGIC_VECTOR (127 downto 0);
begin
b3: keymix port map(ri,rdk,n2);
b2: InSbox7set port map(n2,n1);
b1: keymix port map(n1,rk, ro);

end Behavioral;